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LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 1 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? description the LX1675 is a highly integrated power supply controller ic featuring three voltage mode pwm switching regulator stages with an additional onboard linear regulator driver. two of the constant frequency pwm phases can be easily configured for a single bi-phase high current output or operated as two independently regulated outputs. all outputs (pwm phases and ldo) have separate, programmable soft- start sequencing. this versatility yields either three or four independently regulated outputs with full power sequencing capability giving system designers the ultimate flexibility in power supply design. current limit for each pwm regulator is provided by monitoring the voltage drop across the lower mosfet power stage during conduction, utilizing the rds(on) impedance. this eliminates the need for expensive current sense resistors. once current limit has been reached and persist for 4 clock cycles, the output is shut off and soft start is initialized to force a hiccup mode for protection. high current mosfets can be directly driven to provide an ldo output of 5a and 15a for each pwm controller. this is useful for i/o, memory, termination, and other supplies surrounding today?s micro-processor based designs. the LX1675 accepts a wide range of supply voltage ranging from 4.5v to 24v. each pwm regulator output voltage is programmed via a simple voltage-divider network. the LX1675 design gives engineers maximum flexibility with respect to the mosfet supply. each phase can utilize different supply voltages for efficient use of available supply rails. additionally, when two phases are configured in bi-phase output, the loadshare ? topology can be programmed via inductor esr selection. the split phase operation reduces power loss, noise due to the esr of the input capacitors and allows for reduction in capacitance values while maximizing regulator response time. the internal reference voltage is buffered and brought out on a separate pin to be used as an external reference voltage. important: for the most current data, consult microsemi ?s website: http://www.microsemi.com loadshare is a trademark of microsemi corporation protected by u.s. patents 6,285,571 and 6,292,378 key features ? four independently regulated outputs ? single input supply with wide voltage range: 4.5-24v ? outputs as low as 0.8v generated from a precision internal reference ? selectable pwm frequency of 300khz or 600khz ? buffered reference voltage output ? multiphase output reduces need for large input capacitance at high currents ? integrated high current mosfet drivers ? independent soft-start and power sequencing ? adjustable linear regulator driver output ? no current-sense resistors ? ddr termination compliant ? rohs compliant for pb free applications ? multi-output power supplies ? video card power supplies ? pc peripherals ? portable pc processor and i/o supply product highlight hox 5h vin vout1, 2, 3 fbx eox vin 4.5v to 24v vccl one of 3 pwm sections LX1675 vout4 csx vcx hrx lox ssx vslr pgx agnd ldgd ldfb package order info lq plastic mlpq 38-pin t a ( c) rohs compliant / pb-free 0 to 85 LX1675clq -40 to 85 LX1675ilq note: available in tape & reel. append the letters ?tr? to the part number. (i.e. LX1675clq-tr) l l x x 1 1 6 6 7 7 5 5 www..net
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 2 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? absolute maximum ratings supply voltage (vin , vslr, hrx) ............................................................... -0.3v to 24v supply voltage (vccl) ................................................................................ -0.3 v to 6.0v driver supply voltage (vcx) ........................................................................ -0.3v to 30v current sense inputs (c sx)............................................................................ -0.3 v to 30v error amplifier inputs (fb x , rf2, ldfb) .................................................... -0.3v to 5.5v internal regulator current (i vccl )............................................................................... 50ma output drive peak current source (ho x , lo x ) ................................................ 1a (200ns) output drive peak current sink (ho x , lo x )................................................. 1.5a (200ns) differential voltage: v hox ? v hrx (high side return ) .................................... -0.3v to 6v soft start input (ssx , ssl) ............................................................................- 0.3v to v ref logic inputs ( sf, fs) ..........................................................................-0.3v to v ccl + 0.5v ldo gate drive (ldgd) out put drive can source .................................................. 10ma ldo feedback (ldf b) input .......................................................................................6.0v operating junction temperatur e................................................................................ 150c operating temperature range .......................................................................- 40c to 85c storage temperat ure rang e.........................................................................-65 c to 150 c peak package solder reflow temp. (40 seconds maximum exposure) ......... 260c (+0 -5) note: exceeding these ratings could cause damage to the device. all voltages are with respect to ground. currents are positive into, negative out of specified terminal . limitations affecting transient pulse duration is thermally related to the clamping zener diodes connected to the supply pins, application of maximum voltage will increase current into that pin and increase power dissipation. x denotes respective pin designator 1, 2, or 3. thermal data lq plastic mlpq 38-pin thermal resistance - junction to a mbient , ja 30 to 55 c/w junction temperature calculation: t j = t a + (p d x ja ). the ja numbers are dependent on heat spreading a nd layout considerations for the thermal performance of the device/pc-board system. a ll of the above assume no ambient airflow. package pin out lo2 hr2 ho2 vc2 cs2 sf eo2 ss2 rf2 eo1 fb1 ss3 fb3 eo3 fs cs3 dgnd cs1 vin vccl pg3 lo3 ho3 vc3 vc1 ho1 hr1 lo1 pg1 ldgd vslr ssl ldfb ss1 agnd vref fb2 hr3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 connect bottom to power gnd lq p ackage (top view) rohs / pb-free 100% matte tin lead finish p p a a c c k k a a g g e e d d a a t t a a
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 3 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? functional pin description name description fb1 bi-phase operation: phase 1 and 2 voltage feedback single phase operation: phase 1 voltage feedback, connect to the output through a resistor network to set desired output voltage of phase 1. fb2 bi-phase operation: load sharing voltage sense feedback ? connect filtered phase 2 switching output (pre-inductor) to fb2 to ensure proper current sharing between phase 1 and phase 2. single phase operation: phase 2 voltage feedback, connect to the output through a resistor network to set desired output voltage of phase 2. fb3 phase 3 voltage feedback , connect to the output through a resi stor network to set desired output voltage of phase 3. rf2 bi-phase operation: load sharing voltage sense feedback re ference ? sets reference for current sharing control loop. connecting filtered phase 1 sw itching output (pre-inductor) to rf2 forces the average current in phase 2 to be equal to phase 1. single phase operation: phase 2 voltage reference ? connected to ss2 pin as the reference. eox error amplifier output ? sets external co mpensation for the corresponding phase denoted by ?x?. vin controller supply voltage. vccl for 4.5v < vin < 6v, this pin becomes the input voltage supply for the controller?s internal logic and gate drivers. for vin > 6v this pin is an output of the in ternal 5v regulator that supplies intern al logic, low side gate drivers and high side charge pump capacitor charging, if used. user must provide low esr decoupling capacitor for pulse load currents agnd analog ground reference. dgnd digital/switching ground reference for cu rrent paths of the pwm driver circuits. vslr supply pin for ldo regulator section. ldfb low dropout regulator voltage feedback ? sets the out put voltage of external mosfet via resistor network. ldgd low dropout regulator gate drive ? connects to gat e of external n-mosfet fo r linear regulator supply. ssl ldo enable and soft-start/hiccup capacitor pin - during st art-up, the voltage on this pin ramps from 0v to vref controlling the output voltage of the regulator. an internal 20k ? resistor connected to vref and the external capacitor set the time constant for soft-start f unction. the soft-start function does not in itialize until the supply voltage exceeds the uvlo threshold. sf shared fault - if sf input = logic 1(vccl) and current limit threshold is reached during 4 clock cycles all outputs are shutdown by discharging ss caps to zero and the start-up sequence begins again, this becomes hiccup mode protection with the duty cycle set by the size of the ss capacitor. w hen operated in bi-phase mode, sf must be set high. if sf = logic 0, the other outputs continue to function normally and the faulted output ent ers the hiccup mode for current limit. fs frequency select logic input - connect to ground for 300khz and vccl for 600khz operation. input has 100k ? pull down resistor. vref buffered version of the in ternal 0.8 voltage reference. csx over-current limit set ? connecting a re sistor between csx pin and the drain of the low-side mosfet sets the current- limit threshold for the corresponding phase denoted by ?x?. a minimum of 500 ? must be in series with this input. whenever the current limit threshold is reached for 4 consecutive clock cycles the soft start capacitor is discharged through an internal resistor initiating soft start and hiccup mode. ssx enable & soft-start/hiccup capacitor pin ? during start-up, the voltage on this pin contro ls the output voltage of its respective regulator. an internal 20k ? resistor and the external capacitor set t he time constant for soft-start function. the soft-start function does not initialize until the supply voltage exceeds the uvlo threshold. when an over-current condition occurs, this capacitor is used for the timing of hicc up mode protection. pulling the ss pin below 0.1v disables the corresponding phase denoted by ?x?. vcx pwm high-side mosfet gate driver supply ? connect to separate supply or to boot strap supply to ensure proper high-side gate driver supply voltage. ?x? denotes co rresponding phase. if the phase is not used connect to vcc. hox high side mosfet gate driver ? ?x? denotes corresponding phase. lox low side mosfet gate driver ? ?x? denotes corresponding phase. pgx low-side driver power ground. connects to the source of the bottom n-channel mosfets of each phase, where x denotes corresponding phase. pg1 is the shar ed ground of pwm 1 and pwm 2 low-side drivers. hrx high side driver return, connect this pin to hig h side mosfet source. ?x? denotes corresponding phase. p p a a c c k k a a g g e e d d a a t t a a
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 4 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? electrical characteristics for the LX1675ilq the following specifications apply over the ambient temperature -40c < ta < 85c and for the LX1675clq 0 c 85 c except where otherwise noted and the following test conditions: v in & vslr = 12v, v cx = 17v, hox and lox =3000pf load, fs = 0 (f = 300khz). LX1675 parameter symbol test conditions min typ max units ` switching regulators vin regulator functional 4.5 24 vcx 30 input voltage vccl 6 v operation current i vin static 6 ma feedback voltage internal reference v fb 4.5v < vin < 12v 0.784 0.816 v line regulation -1 1 % load regulation system level measurement, closed loop -1 1 % high side minimum pulse width load = 3000pf 50 ns 600khz 74 % maximum duty cycle pwm dc 85 % lox minimum on time vlox @ 25c from 3v going high to 1v going low 180 225 320 ns buffered reference voltage v ref max load current 0.5ma 0.778 0.822 v ` error amplifier input offset voltage v os common mode input voltage = 1v -7.0 7.0 mv dc open loop gain 70 db unity gain bandwidth av ugbw 10 mhz high output voltage v oh i source = 2ma 3.75 5.0 v low output voltage v ol i sink = 100a 100 mv input common mode range input offset voltage < 20mv 0.1 3.5 v input bias current i in 0v and 3.5v common mode voltage 100 na ` current sense cs bias current (source) i set v csx = -0.2v, v pgx = 0v @ 25c 48 55 62 a cs trip threshold v trip referenced to v csx , v pgx = 0v 3 mv cs delay (blanking) t csd 150 ns v ih any pwm output activating current limit for more than 4 clock cycles, soft starts all pwm outputs 2 shared fault mode v il current limit event of one pwm does not effect the continued function of the two other pwm regulators 0.8 v ` output drivers ? n channel mosfets low side driver operating current i vccl static 2.5 ma high side driver operating current i vcx static 3 ma drive rise and fall time t r/f c l = 3000pf 50 ns dead time ? high side to low side or low side to high side t dead drive load = 3000pf, v drive < 1v 50 ns high side driver voltage drive high i hox = 20ma, vcx ? hrx = 5.0v 4.8 4.9 drive low v hox i hox = -20ma, vcx ? hrx = 5.0v 0.1 0.2 v low side driver voltage drive high i lox = 20ma, vccl ? pgx = 5.0v 4.8 4.9 drive low v lox i lox = -20ma, vccl ? pgx = 5.0v 0.1 0.2 v high side driver current i hox vcx ? hrx = 5.0v, capacitive load, pw < 200ns 1 a peak low side driver current i lox vccl ? pgx = 5.0v, capacitive load, pw < 200ns 1.5 a peak maximum load qg max 50 nc ` oscillator v fs <0.8v @ 25c 255 300 345 khz pwm switching frequency f sw v fs >2v @ 25c 510 600 690 khz ramp amplitude vramp 1.6 vpp e e l l e e c c t t r r i i c c a a l l s s
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 5 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? electrical characteristics (continued) for the LX1675ilq the following specifications apply over the ambient temperature -40c < ta < 85c and for the LX1675clq 0 c < t a < 85 c except where otherwise noted and the following test conditions: v in & vslr = 12v, v cx = 17v, hox and lox =3000pf load, fs = 0 (f = 300khz). LX1675 parameter symbol test conditions min typ max units ` internal 5v regulator regulated output vccl internal + external load: 0ma < i vccl < 50ma 4.5 5.5 v ` uvlo and soft-start (ss) start-up threshold (vcx, vccl, vin) rising 3.75 4.38 v hysteresis 0.30 v ss input resistance r ss 20 k ? ss shutdown threshold v shdn 100 mv hiccup mode duty cycle c ss = 0.1f 6 % ` linear regulator controller voltage reference tolerance v ldfb = 0.8v, c out = 330f 3 % ldo supply ivslr vslr = 12v 4 ma voh, output source current = 0.5ma 9.0 ldo gate drive voh, output source current = 10ma 7.35 v source current i ldgd v ldgd = 7.5v 10 ma sink current i ldgd v ldgd = 0.4v 0.25 ma ldo output voltage range v out4 0.8 5.25 v regulator disable threshold v ssl 100 mv line regulation note 2, 1v < v ldo ? v out4 < 10v, i vout4 = 50ma -1 1 % load regulation note 2 -1 1 % ` logic inputs threshold logic high 2 v threshold logic low 0.8 v fs,sf pulldown resistance 100 k ? ` thermal shutdown tsd hiccup mode operation at limit 160 c die temperature note 1: x = phase 1, 2, 3 note 2: system level measurement; closed loop e e l l e e c c t t r r i i c c a a l l s s
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 6 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? simplified block diagram cs comp + - amplifier/ compensation + - error comp + - v ref hiccup ramp oscillator +5v regulator lx esr c out c in +5v out x r set vccl lox hox vcx csx fbx agnd pwm i set eox vin pgx r1 ssx r2 tsd f r s +5v css 500k hrx bg vref q r s 50ua + + 20k + - 100mv fault ssmsk clk 4 cycle counter ramp clk ss comp uvlo vin vin fs sf figure 1 ? typical block diagram for phases 1, and 3 v ref c in v o u t 4 ldgd ldfb sf ssl f css 500k + 20k + - ldoflt ldoea vin vslr 9.6v regualtor figure 2 ? ldo controller block diagram b b l l o o c c k k d d i i a a g g r r a a m m
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 7 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? simplified block diagram cs comp + - amplifier/ compensation + - error comp + - v ref hiccup ramp oscillator +5v regulator l2 esr c out c in +5v out 2 r set vccl lo2 ho2 vc2 cs2 fb2 agnd pwm i set eo2 vin pgx ss2 tsd f r s +5v css 500k hr2 bg vref q r s 50ua + + 20k + - 100mv fault ssmsk clk 4 cycle counter ramp clk ss comp uvlo vin vin lpf2 rf2 lpf1 phase 1 fs figure 3 ? block diagram of phase 2 connected in loadshare mode b b l l o o c c k k d d i i a a g g r r a a m m
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 8 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? application ciruit q3a fds6898a q3b fds6898a q1a fds6898a q1b fds6898a q4a fds6898a q4b fds6898a 16v + c7 470uf +vin sf c6 0.1uf 16v vref rtn +vin r12 24.3k c22 1.5nf r13 14.3k c32 4.7uf cr3 mbr 0530 cr1 mbr 0530 cr2 mbr 0530 16v + c21 470uf c29 470pf c13 0.1uf 16v + c2 470uf tp20 tp21 tp15 tp16 +1.8v out tp25 tp28 16v + c4 470uf r19 20 16v + c11 470uf +vin +2.5v r14 2.00k r8 2.00k tp7 l1 6.8uh c1 0.1uf c14 0.22uf c18 0.33uf l2 6.8uh tp18 r18 24.3k r11 45.3k r21 20 16v tp19 r6 100k l3 6.8uh tp30 c19 22pf r22 20 c9 4.7uf tp31 r10 24.3k r1 2.10k r20 0.0 + c8 470uf r9 21.0k r5 100k tp6 c15 22pf c16 1.2nf tp9 c23 0.1uf c17 1.2nf tp22 tp23 + c27 100uf c10 4.7uf r4 2.00k out +1.2v out +2.5v + c12 470uf +vin +2.5v +vin c20 1.5nf r7 45.3k +vin fs 25v tp33 tp5 tp4 tp3 tp8 tp10 tp11 tp12 tp32 tp38 tp13 c25 1.5nf r17 88.7k tp17 r16 45.3k r15 100k c26 22pf c24 1.2nf tp26 tp27 tp34 via tp35 tp36 q2 irf7822 r2 1.69k u2 LX1675clq cs2 5 sf 6 eo2 7 fb2 8 ss2 9 rf2 10 eo1 11 fb1 12 ldgd 13 vslr 14 ssl 15 ldfb 16 ss1 17 agnd 18 vref 19 ss3 20 fb3 21 eo3 22 fs 23 cs3 24 dgnd 25 cs1 26 vin 27 vccl 28 pg3 29 lo3 30 vc3 33 hr3 31 ho3 32 vc1 34 ho1 35 hr1 36 lo1 37 pg1 38 lo2 1 hr2 2 ho2 3 vc2 4 out +3.3v tp29 tp37 tp24 tp1 + c5 470uf tp2 25v 16v c28 0.33uf figure 4 ? four separate voltage outputs with sequential po wer up sequence. all high-side mosfet drivers bootstrapped to v in . a a p p p p l l i i c c a a t t i i o o n n s s
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 9 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? theory of operation g eneral d escription the LX1675 is a voltage-mode pulse-width modulation controller integrated circuit. the internal ramp generator frequency is set to 300khz or 600khz by the fs logic input. the device has external compensation, for more flexibility of output current magnitude. u nder v oltage l ockout (uvlo) at power up, the LX1675 monitors the supply voltage at the vccl pin. the vin supply voltage has to be sufficient to produce a voltage greater that 4.4 volts at the vccl pin before the controller will come out of the under-voltage lock-out state. the soft-start (ss) pin is held low to prevent soft-start from beginning and the oscillator is disabled and all mosfets are held off. s oft -s tart once the vccl output is above the uvlo threshold, the soft- start capacitor begins to be charged by the reference through a 20k internal resistor. the capacito r voltage at the ss pin rises as a simple rc circuit. the ss pin is connected to the error amplifier?s non-inverting input that controls the output voltage. the output voltage will follow the ss pin voltage if sufficient charging current is provided to the output capacitor. the simple rc soft-start allows the output to rise faster at the beginning and slower at the end of th e soft-start interval. thus, the required charging current into the output capacitor is less at the end of the soft-start interval. a comparator monitors the ss pin voltage and indicates the end of soft-start when ss pin voltage reaches 95% of v ref . o ver -c urrent p rotection (ocp) and h iccup the LX1675 uses the r ds(on) of the lower mosfet, together with a resistor (r set ) to set the actual current limit point. the current sense comparator senses the mosfet current 50ns after the lower mosfet is switched on in order to reduce inaccuracies due to ringing. a current source supplies a current (i set ), whose magnitude is 50a. the set resistor r set is selected to set the current limit for the application. r set should be connected directly at the lower mosfet drain and the source needs a low impedance return to get an accurate measurement across the low resistance r ds(on) . when the sensed voltage across rds (on) plus the set resistor voltage drop exceeds the 0.0volt, v trip threshold, the ocp comparator outputs a signal to reset the pwm latch on a cycle by cycle basis until the current limit c ounter has reached a count of 4. after a count of 4 the hiccup mode is started. the soft-start capacitor (c ss ) is discharged slowly (14 times slower than when being charged up by r ss ). when the voltage on the ss pin reaches a 0.1v threshold, hiccup finishes a nd the circuit soft-starts again. during hiccup both mosfets for that phase are held off. the shared fault, sf logic input, allo ws all phases to be totally independent if the sf pin is grounded. if the sf pin is tied to vccl then when one phase has a fault and goes into the hiccup mode, all phases, including the ldo output will go into the hiccup mode together. hiccup is disabled during the soft-s tart interval, allowing start up with maximum current. if the rate of rise of the output voltage is too fast, the required charging current to the output capacitor may be higher than the current limit setting. in this case, the peak mosfet current is regulated to the limit-current by the current-sense comparator. if the mosfet current still reaches its limit after the soft-start finishes, the hiccup is tr iggered again. when the output has a short circuit the hiccup circuit ensures that the average heat generation in both mosfets and the average current is much less than in normal operation. over-current protection can also be implemented using a sense resistor, instead of using the r ds(on) of the lower mosfet, for greater set-point accuracy. o scillator f requency an internal oscillator has a se lectable switching frequency of 300khz or 600khz set by the fs logic input pin. connect fs to ground for 300khz and to vccl for 600khz operation. t heory of o peration for a b i -p hase , l oad share configuration the basic principle used in loadshare, in a multiple phase buck converter topology, is that if multiple, identical, inductors have the same identical voltage impressed across their leads, they must then have the same identical current passing through them. the current that we would like to bala nce between inductors is mainly the dc component along with as mu ch as possible the transient current. all inductors in a multi phase buck converter topology have their output side tied together at the output filter capacitors. therefore this side of all the inductors have the same identical voltage. if the input side of the inductors can be forced to have the same equivalent dc potential on this lead, then they will have the same dc current flowing. to achieve this requirement, phase 1 will be the control phase that sets th e output operating voltage, under normal pwm operation. to force the current of phase 2 to be equal to the current of phase 1, a second feedback loop is used. phase 2 has a low pass filter connected from the input side of each inductor. this side of the inductors has a square wave signal that is proportional to its duty cycle. the out put of each lpf is a dc (+ some ac) signal that is propor tional to the magnitude and duty cycle of its respective inductor si gnal. the second feedback loop will use the output of the phase 1 lpf as a reference signal for an error amplifier that will compare this reference to the output of the phase 2 lpf. this error signal will be amplified and used to control the pwm circuit of phase 2. therefore, the duty cycle of phase 2 will be set so that the equivalent voltage potential will be forced across the phase 2 inductor as compared to the phase 1 inductor. this will force the current in the phase 2 inductor to follow and be equal to the current in the phase 1 inductor. there are four methods that can be used to implement the loadshare feature of the LX1675 in the bi-phase mode of operation. a a p p p p l l i i c c a a t t i i o o n n s s
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 10 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? theory of operation (continued) b i -p hase , l oad share (esr m ethod ) the first method is to change the ratio of the inductors equivalent series resistance, (esr). as can be seen in the previous example, if the offset error is zero and the esr of the two inductors are identical, then the two inductor currents will be identical. to change the ratio of current between the two inductors, the value of the indu ctor?s esr can be changed to allow more current to flow through one inductor than the other. the inductor with the lower esr value will have the larger current. the inductor currents are directly proportional to the ratio of the inductor?s esr value. the following circuit descripti on shows how to select the inductor esr for each phase where a different amount of power is taken from two different input power supplies. a typical setup will have a +5v power supply connected to the phase 1 half bridge driver and a +3.3v power supply connected to the phase 2 half bridge driver. the combined power output for this core voltage is 18w (+1.5v @ 12a). for this example the +5v power supply will supply 7w and the +3.3v power supply will supply the other 11w. 7w @ 1.5v is a 4.67a current through the phase 1 inductor. 11w @ 1.5v is a 7.33a current through the phase 2 inductor. the ratio of inducto r esr is inversely proportional to the power level split. 1 i 2 i 2 esr 1 esr = the higher current inductor will have the lower esr value. if the esr of the phase 1 inductor is selected as 10m , then the esr value of the phase 2 inductor is calculated as: m ? 4 . 6 m ? 10 a 33 . 7 a 67 . 4 = ? ? ? ? ? ? depending on the required accuracy of this power sharing; inductors can be chosen from standard vendor tables with an esr ratio close to the required values. inductors can also be designed for a given application so that there is the least amount of compromise in the inductor?s performance. 1.5v @ 12a 18w 6.4m 4.67a 7.33a 10m 1.5v + 46.7mv l1 l2 +5v @ 7w +3.3v @ 11w figure 7 ?loadshare using inductor esr b i -p hase , l oad share (f eedback d ivider m ethod ) sometimes it is desirable to use th e same inductor in both phases while having a much larger current in one phase versus the other. a simple resistor divide r can be used on the input side of the low pass filter that is taken off of the switching side of the inductors. if the phase 2 current is to be larger than the current in phase 1; the resistor divider is placed in the feedback path before the low pass filter that is connected to the phase 2 inductor. if the phase 2 current needs to be less than the current in phase 1; the resistor divider is then placed in the feedback path before the low pass filter that is connected to the phase 1 inductor. as in figure 7, the millivolts of dc offset created by the resistor divider network in the feedback path, appears as a voltage generator between the esr of the two inductors. a divider in the feedback path from phase 2 will cause the voltage generator to be positive at phase 2. with a divider in the feedback path of phase 1 the voltage generator becomes positive at phase 1. the phase with the pos itive side of the voltage generator will have the larger current. systems that operate continuously above a 30% power level can use this method. a down side is that the current difference between the two inductors still flows during a no lo ad condition. this produces a low efficiency condition during a no load or light load state, this method should not be used if a wide range of output power is required. the following description and figure 8 show how to determine the value of the resistor divider network required to generate the offset voltage necessary to produce the different current ratio in the two output inductors. the power sharing ratio is the same as that of figure 7. the offset voltage generator is symbolic for the dc voltage offset between phase 1 & 2. this voltage is generated by small changes in the duty cycle of phase 2. the output of the lpf is a dc voltage proportional to the duty cycle on its input. a small amount of attenuation by a resistor divider before the lpf of phase 2 will cause the duty cycle of phase 2 to increase to produce the added offset at v2. the high dc gain of the error amplifier will force lpf2 to always be equal to lpf1. the following calculations determine the value of the resistor divider necessary to satisfy this example. a a p p p p l l i i c c a a t t i i o o n n s s
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 11 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? theory of operation (continued) l1, switch side l2, switch side 100 not used 62k 4700pf + - 62k 4700pf 62k tbd 100 offset voltage generator - + esr l1 10m esr l2 10m v o u 1.5v @ 12 a 18 w resistor divider resistor divider phase 2 error amp phase 1 phase 2 v1 v2 1.5v +73.3mv 1.5v +46.7mv 7.33a 4.67a +5v @ 7w +3.3v @ 11w lpf1 lpf2 fb2 rf2 pwm input figure 8 ? loadshare using feedb ack divider offset where v1 = 1.5467 ; v2 = 1.5733 and 2 v 1 v k = then k 5.814 k 1 100 k tbd = ? = a a p p p p l l i i c c a a t t i i o o n n s s
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 12 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? theory of operation (continued) b i -p hase , l oad share (p roportional m ethod ) the best topology for generating a current ratio at full load and proportional between full load and no load is shown in figure 9. the dc voltage difference between lpf1 and vout is a voltage that is proportional to th e current flowing in the phase 1 inductor. this voltage can be amplified and used to offset the voltage at lpf2 through a larg e impedance that will not significantly alter the characteristics of the low pass filter. at no load there will be no offset voltage and no offset current between the two phases. this will give th e highest efficiency at no load. also a speed up capacitor can be used between the offset amplifier output and the negative input of the phase 2 error amplifier. this will improve the transient response of the phase 2 output current, so that it will share more equally with phase 1 current during a transient condition. the use of a mosfet input amplifier is required for the buffer to prevent loading the low pass filter. the gain of the offset amplifier, and the value of ra and rb, will determine the ratio of currents between the phases at fu ll load. two external amplifiers are required or this method. l1, switch side l2, switch side 62k + - 62k 4700pf 62k offset voltage generator - + esr l1 10m esr l2 10m v o u 1.5v @ 12 a 18 w phase 2 error amp phase 1 phase 2 v 1 v2 1.5v +73.3mv 1.5v +46.7mv 7.33a 4.67a +5v @ 7w +3.3v @ 11w lpf2 + - + - 1m 4700pf lpf1 offset amp vos rf rin ra rb rf2 fb2 pwm input figure 9 ? loadshare using proportional control a a p p p p l l i i c c a a t t i i o o n n s s
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 13 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? theory of operation (continued) the circuit in figure 9 sums a current through a 1m resistor (rb) offsetting the phase 2 error amplifier to create an imbalance in the l1 and l2 currents. although there are many ways to calculate component valu es the approach taken here is to pick ra, rb, rin, vout, and inductor esr. a value for the remaining resistor rf can then be calculated. the first decision to be made is the current sharing ratio. follow the previous examples to understand the basics of loadshare. the most common reason to imbalance the currents in the two phases is because of limitations on the available power from the input rails for each phase. use the available input power and tota l required output power to determine the inductor currents for each phase. all references are to figure 9 1) calculate the voltages v1 and v2. vout esr 1 l current 1 l 1 v + = vout esr 2 l current 2 l 2 v + = 2) select values for ra and rb (ra is typically 62k ; rb is typically 1m ) 3) calculate the offset voltage vos at the output of the offset amplifier () rb ra ra 1 v 2 v 2 v vos + ? ? = ? ? ? ? ? ? 4) calculate the value for rf (select a value for rin typically 5k ) ? ? ? ? ? ? ? ? = 1 v vout vout vos rin rf due to the high impedances in this circuit layout can affect the actual current ratio by allowing some of the switching waveforms to couple into the current summing path. it may be necessary to make some adjustment in rf afte r the final layout is evaluated. also the equation for rf requires very accurate numbers for the voltages to insure an accurate result. b i -p hase , l oad share (s eries r esistor m ethod ) a fourth but less desirable way to produce the ratio current between the two phases is to add a resistor in series with one of the inductors. this will reduce the current in the inductor that has the resistor and increase the current in the inductor of the opposite phase. the example of figure 7 can be used to determine the current ratio by adding the value of the series resistor to the esr value of the inductor. the added resistance will lower the overall efficiency loadshare error sources with the high dc feedback gain of this second loop, all phase timing errors, r ds(on) mismatch, and voltage differences across the half bridge drivers are removed from the current sharing accuracy. the errors in the current sharing accuracy are derived from the tolerance on the inductor?s esr and the input offset voltage specification of the error amplifier. the equivalent circuit is shown next for an absolute worst ca se difference of phase currents between the two inductors. vout + - esr l2 esr l1 phase 2 phase 1 offset error 5mv v1 v2 figure 10 ? error amplitude nominal esr of 6m ? . esr 5% max offset error = 6mv +5% esr l1 = 6.3 m ? -5% esr l2 = 5.7 m ? 1 esrl v - 1 v a 12 current 1 phase if out = = mv 75.6 10 6.3 12 v 1 v 3 out = = ? ? mv .6 1 8 mv 6 1 v 2 v = + = a 32 14. 10 x 5.7 10 x .6 1 8 2 l esr v - 2 v current 2 phase 3 3 out = = = ? ? phase 2 current is 2.32a greater than phase 1. input bias current also c ontributes to imbalance. a a p p p p l l i i c c a a t t i i o o n n s s
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 14 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? application note o utput i nductor the output inductor should be selected to meet the requirements of the output voltage ripple in steady-state operation and the inductor current slew-rate during transient. the peak-to- peak output voltage ripple is: ripple ripple i esr v = where s d l v v i out in f ? = i is the inductor ripple current, l is the output inductor value and esr is the effective series resistance of the output capacitor. i should typically be in the range of 20% to 40% of the maximum output current. higher inductance results in lower output voltage ripple, allowing slightly higher esr to satisfy the transient specification. higher inductance also slows the inductor current slew rate in response to the load-current step change, i, resulting in more output-capacitor voltage droop. when using electrolytic capacitors, the cap acitor voltage droop is usually negligible, due to the large capacitance the inductor-current rise and fall times are: () out in rise v v i l t ? = and out fall v i l t = .the inductance value can be calculated by s d i v v l out in f ? = o utput c apacitor the output capacitor is sized to meet ripple and transient performance specifications. effective series resistance (esr) is a critical parameter. when a step load current occurs, the output voltage will have a step that equals the product of the esr and the current step, i. in an advanced microprocessor power supply, the output capacitor is usually select ed for esr instead of capacitance or rms current capability. a capacitor that satisfies the esr requirements usually has a larger capacitance and current capability than strictly needed. the allowed esr can be found by: ( ) ex ripple v i i esr < + where i ripple is the inductor ripple current, i is the maximum load current step change, and v ex is the allowed output voltage excursion in the transient. electrolytic capacitors can be used for the output capacitor, but are less stable with age than tantalum capacitors. as they age, their esr degrades, reducing the system performance and increasing the risk of failure. it is recommended that multiple parallel capacitors be used, so that, as esr increase with age, overall performance will still meet the processor?s requirements. there is frequently strong pressu re to use the least expensive components possible; however, this could lead to degraded long- term reliability, especially in the case of filter capacitors. microsemi?s demonstr ation boards use the cde polymer al-el (esre) filter capacitors, which are aluminum electrolytic, and have demonstrated re liability. the os-con series from sanyo generally provides the very best performance in terms of long term esr stability and general reliability, but at a substantial cost penalty. the cde polymer al-el (esre) filter series provides excellent esr performance at a reasonable cost. beware of off- brand, very low-cost filter capa citors, which have been shown to degrade in both esr and general electrolytic characteristics over time. a a p p p p l l i i c c a a t t i i o o n n s s
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 15 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? application note (continued) i nput c apacitor the input capacitor and the input inductor, if used, are to filter the pulsating current generated by the buck converter to reduce interference to other circuits connected to the same 5v rail. in addition, the input capacitor provides local de-coupling for the buck converter. the capacitor sh ould be rated to handle the rms current requirements. the rms current is: d) d(1 i i l rms ? = where i l is the inductor current and d is the duty cycle. the maximum value occurs when d = 50% then i rms =0.5i l . for 5v input and output in the range of 2 to 3v, the required rms current is very close to 0.5i l . s oft -s tart c apacitor the value of the soft-start capacitor determines how fast the output voltage rises and how large the inductor current is required to charge the output capacitor. the output voltage will follow the voltage at the ss pin if the re quired inductor current does not exceed the maximum allowable curre nt for the inductor. the ss pin voltage can be expressed as: ( ) ? ? = ref where r ss and c ss are the soft-start resistor and capacitor. the current required to charge the output capacitor during the soft start interval is. dt dvss cout iout = taking the derivative with respect to time results in ss ss c t/r e rsscss vrefcout iout ? = and at t = 0 rsscss vrefcout ax im = the required inductor current for the output capacitor to follow the soft start voltage equals the required capacitor current plus the load current. the soft-start ca pacitor should be selected to provide the desired power on sequencing and insure that the overall inductor current does not exceed its maximum allowable rating. values of c ss equal to 0.1f or greater are unlikely to result in saturation of the output inductor unless very large output capacitors are used. o ver -c urrent p rotection current limiting occurs at current level i cl when the voltage detected by the current sense comparator is greater than the current sense comparator threshold, v trip (0.0 volts). set set cl ds(on) trip i?r-i?r =v so, cl ds(on) cl ds(on) set set ir ir r i50a == example: for 10a current limit, us ing fds6670a mosfet (10m r ds(on) ): set 6 10 0.010 r2.00k ? 1% 50 10 ? == note: if r set is 0.0 or the csx pin has become shorted to ground the device will be continuously in the current limit mode. if the csx pin is left open then the current limit will never be enabled. a resistor should be selected fo r the maximum desired current limit and this should also provide enou gh current to charge up the output filter capacitance during the soft-start time. the current limit comparator is followed by a counter that does not allow the hiccup mode until the current limit condition has existed for 4 pwm cycles. if the current limit condition goes away after a count of 2 the counter will be reset. this mode will prevent a single cycle current or noise gl itch from starting the hiccup mode current limit. a a p p p p l l i i c c a a t t i i o o n n s s
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 16 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? application note (continued) o utput e nable the LX1675 mosfet driver outputs are shut off by pulling the soft-start pin below 0.1v. the ldo voltage regulator has its own soft-start pin: ssl, that is the same as any of the other switching phases for control of its output voltage shut down. p rogramming t he o utput v oltage the output voltage is sensed by the feedback pin (fb x ) which is compared to a 0.8v reference. the output voltage can be set to any voltage above 0.8v (and lower than the input voltage) by means of a resistor divider r1-r2 (see figure 1). ) /r r (1 v v 2 1 ref out + = note: this equation is simplified and does not account for error amplifier input current. keep r 1 and r 2 close to 1k (order of magnitude). an 18 for more information see micr osemi application note 1307: lx1671 product design guide . the LX1675 and lx1671 have the same functionality and this information will be applicable. ddr v tt t ermination v oltage double data rate (ddr) sd ram requires a termination voltage (v tt ) in addition to the line driver supply voltage (vddq) and receiver supply voltage (vdd). although it is not a requirement vdd is generally equal to vddq so that only v tt and vddq are required. the LX1675 can supply both voltages by using two of the three pwm phases. since the currents for v tt and (vdd plus vddq) are quite often several amps, (2a to 6a is common) a switching regulator is a logical choice v tt for ddr memory can be generated with the LX1675 by using the positive input of the phase 2 error amplifier rf2 as a reference input from an external reference voltage v ref which is defined as one half of vddq. using v ref as the reference input will insure that all voltages are correct and track each other as specified in the jedec (eia/jesd8-9a) specification. the phase 2 output will then be equal to v ref and track the vddq supply as required. when an external reference is used the soft start will not be functional for that phase see microsemi application note 1306: ddr sdram memory termination for more details. a a p p p p l l i i c c a a t t i i o o n n s s
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 17 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? application note considerations 1. the power n-mosfet transistor?s total gate charge spec, (qg) should not exceed 50nc. this condition will guarantee operation over the specified ambient temperature range with 600khz operating frequency. the qg value of the n- mosfet is directly related to the amount of power dissipation inside the ic package, from the three sets of mosfet drivers. the equation relating qg to the power dissipation of a mosfet driver is: pd = f * qg * vd . f = 300khs and vd is the suppl y voltage for the mosfet driver. the three bottom mosfet drivers are powered by the vccl pin that is connected to +5v. the upper mosfet drivers are connected to a bootstrap supply generated by its output bridge. the bootstrap supply will ride on top of the vin rail. depending on the thermal environment of the application circuit, the qg value of the n-mosfets will have to be less than the 50nc va lue. a typical configuration of the input voltage rails to generate the output voltages required by having the vin suppl y on all phases. at the max qg value, the three bottom mosfet drivers will dissipate 75mw each. the upper mosfet drivers for all three phases will also operate off of +5volts. their dissipation is 75mw each. the total power dissipation for all gate drives is 450mw. icc x vcc =15ma x 5 v= 75mw. total package power dissipation = 525mw. us ing the thermal equation of: tj = ta + pd * oja, the junction temperature for this ic package is = 23 + .525 * 85 which = 68c. this means that the ambient temperature rise has to be less than 82c. at 600khz the switching losses double so the ambient temperature rise has to be less than 44c. 2. the soft-start reference input has a 100mv threshold, above which the pwm starts to operate. the internal operating reference level is set at 800mv. this means that the output voltage is 12.5% low when the pwm becomes active. this starts each phase up in the cu rrent limit mode without hiccup operation. if more than one ph ase is using the 5v rail for conversion, then their soft-sta rt capacitor values should be changed so that the two phases do not start up together. this will help reduce the amount of 5v input capacitance required. also the vccl pin should have sufficient decoupling capacitance to keep from drooping back below the uvlo set point during start up. 3. it should be noted here that if the vin power supply voltage falls between 4.5v to 6.0v the vin pin and the vccl pin should be connected together . if the vin power supply voltage is greater than 6v then the two pins are kept separate and vccl becomes a 5v output supply for the bootstrap capacitors. the uvlo is looking for the voltage at the vccl pin to be above 4.4v to start up. 4. when phases 1 and 2 are used in the bi-phase mode to current share into the same output load, the phase 2 current is forced to follow the phase 1 current. it is important to use a larger soft- start capacitor on phase 2 than phase 1 so that the phase 1 current becomes active before phase 2 becomes active. this will minimize any start up transient. it is also important to disable phase 1 and 2 at the same time. disabling phase 1 without disabling phase 2, in th e bi-phase mode, allows phase 2 turn on and off randomly because it has lost its reference. 5. the maximum output voltage when using loadshare is limited by the input common mode voltage of the error amplifier and cannot exceed th e input common mode voltage. 6. a resistor has been put in series with the gate of the ldo pass transistor to reduce the output noise level. the resistor value can be changed to optimize the ou tput transient response versus output noise. 7. the ldo controller inside the ic uses the voltage at vslr pin as the drive voltage. this pin should be connected to the vin voltage to insure reliable operation of the ldo controller. an additional decoupling capacitor can be connected to this pin to eliminate any high frequency noise. 8. the ldo controller has its own soft-s tart pin so that its turn on delay can be set so that the volta ge rail connected to its pass transistor has had time to come up first. this will allow a smooth ramp up of the ldo voltage rail. the voltage rail for the ldo pass transistor can come from any of the other pwm phases if desirable. a a p p p p l l i i c c a a t t i i o o n n s s
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 18 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? package dimensions lq 38-pin plastic mlpq (5x7mm ep) e a1 a3 e d a b 1 2 3 e2 d2 l m illimeters i nches dim min max min max a 0.80 1.00 0.031 0.039 a1 0 0.05 0 0.002 a3 0.20 ref 0.008 ref b 0.18 0.30 0.007 0.011 d 5.00 bsc 0.196 bsc d2 3.00 3.25 0.118 0.127 e 7.00 bsc 0.275 bsc e2 5.00 5.25 0.196 0.206 e 0.50 bsc 0.019 bsc l 0.30 0.50 0.012 0.020 note: dimensions do not include mold flash or protrusions; these shall not exceed 0.155m m(0.006?) on any side. lead dimension shall not include solder coverage. recommended solder pad layout 3.15mm 4.10mm 5.50mm 7.50mm 6.10mm 5.20mm 0.25mm 0.50mm m m e e c c h h a a n n i i c c a a l l s s
LX1675 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 19 copyright ? 2004 rev. 1.2a, 2006-02-16 www. microsemi . com multiple output loadshare? pwm tm ? notes production data ? information contained in this document is proprietary to microsemi and is current as of publication date. this document may not be modified in any way without the express written consent of microsemi. product processing does not necessarily include testing of all parameters. microsemi reserves th e right to change the configuration and performance of the product and to discontinue product at any time. n n o o t t e e s s

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